Akihisa YOKOYAMA Hitoshi INOUE Hiroshi HARADA
In this paper we propose a new reconfigurable signal processing platform for SDR, having capability to change its processing parameters dynamically. On our proposed platform, while the wiring and processing scheme remain fixed, processing parameters and connections between processing modules together with the associated dataflow can be changed. We also demonstrate that our proposed signal processing platform has the new ability of easily composing new signal processing models dynamically, simultaneously with other tasks, and attaining high efficiency of logic usage.
Yoshio KUNISAWA Naohiro SAHARA Hiroshi SHIRAI Hisato IWAI
In software defined radio systems, placing the analog-to-digital converter (ADC) near the antenna part in the block diagram of the receiver is desired to improve the flexibility of the system. The radio frequency (RF) sampling method, in which the received signal is sampled at the RF stage, realizes such structure. The undersampling is a potential method to sample the RF signal using the existing consumer ADCs because high speed ADCs are required in the traditional methods, such as Nyquist sampling or the oversampling of the RF signal. This paper presents a technique to determine the minimum sampling frequency to undersample the separated multiple wireless systems simultaneously. In addition, this paper proposes a frequency selecting scheme that enables selection of a lower sampling frequency by receiving at least the desired transmission channels in the wireless system signals. This paper also provides a result of performance analysis of the proposed scheme.
Kazunori AKABANE Hiroyuki SHIBA Munehiro MATSUI Kiyoshi KOBAYASHI Katsuhiko ARAKI
Software defined radio (SDR) mobile terminals that can access multiple wireless communication systems are the trend of the future. An SDR wideband mobile terminal must be capable of high-speed data processing and low power consumption. We focused on reconfigurable processors with these features. To evaluate the performance of reconfigurable processors for SDR wideband mobile terminals, we developed and evaluated software that runs on a reconfigurable processor for the IEEE 802.11a wireless local area network (LAN) baseband part, which requires high-speed data processing. This paper describes the configuration of the SDR IEEE 802.11a software for the reconfigurable processor and its performance evaluation results. Moreover, we showed the requirements for applying the reconfigurable processor to SDR wideband mobile terminals, and confirmed that the reconfigurable processor could be applied to SDR mobile terminals by slight progresses.
Tomoya TANDAI Toshihisa NABETANI Kiyoshi TOSHIMITSU Hiroshi TSURUMI
The next-generation wireless networks will bring users with Software Defined Radio (SDR) terminals seamless mobility and ubiquitous computing through heterogeneous networks. This paper proposes a soft-prioritization based system selection algorithm performed by SDR terminal and investigates the effectiveness of the soft-prioritization based system selection by using a concrete simulation model. To maximize the quality of service (QoS), wireless communication systems are prioritized on the basis of criteria for system selection such as data rate, channel quality and cost, and should be dynamically changed. However, frequent inter-system handovers based on hard-prioritization are undesirable in view of interrupting and dropping, particularly for real-time traffic and managing channel capacities. Wireless communication systems are softly prioritized in the soft-prioritization based system selection algorithm, and therefore inter-system handovers between systems with the same priority aren't initiated. To elucidate the validity of the soft-prioritization based system selection algorithm, a system simulation model consisting of five wireless communication systems is employed. Simulation results confirm that the soft-prioritization system selection algorithm offers higher performance in terms of the number of inter-system handovers and throughput of best effort traffic.
Noriyoshi SUZUKI Kenji ITO Tsutayuki SHIBATA Nobuo ITOH
In this paper, we propose a new concept of receiver structure with diversity reception technique to realize multi-service simultaneous reception, which shares diversity branches between receiving communication services. In the proposed receiver structure, each diversity branch selects the receiving services dynamically according to channel states, and each communication service is always selected by at least one branch to realize multi-service simultaneous reception. A basic algorithm is also described to select combinations of a diversity branch and a receiving communication service. The total number of branches decreases and the effective number of branches per communication service increases, by sharing the branches between communication services in the proposed receiver. Simulation results are shown that the proposed diversity receiver achieves both complexity reduction and performance improvement.
Gweon-Do JO Min-Joung SHEEN Seung-Hwan LEE Kyoung-Rok CHO
As the code division multiple access (CDMA) based third generation cellular infrastructure requires high performance signal processing in a baseband modem, an application-specific integrated circuit or a field-programmable gate array has commonly been used for chip rate processing. In this paper, the use of digital signal processors (DSP) is explored for a cdma2000 and a wideband CDMA channel modem with the goal of increasing flexibility. The design concepts of the prototype software-defined radio platform we implemented to estimate the potential and feasibility of commercial SDR platforms are presented. We discuss the hardware and software architecture of the platform, considerations for reconfigurability, and the test results. We also address practical issues for real-time chip rate processing and optimization schemes of DSP software, and provide detailed measurement results of DSP performance.
A very long instruction word (VLIW) digital signal processor (DSP), called ODiN, which could execute six instructions in a single cycle simultaneously, is designed and fabricated using 0.25 µm 1-ploy 5-metal standard cell static CMOS process. The ODiN core delivers maximum 600 MIPS with 100 MHz system clock. In order to achieve high performance operation, the designed core includes compact register files, orthogonal instruction set, single cycle operations for most instructions, and parallel processing based on software scheduling. In addition, a Viterbi decoder processor and a FFT processor that are embedded make it possible to implement software defined radio (SDR) applications efficiently.
This paper discusses the implementation of multi-band digital intermediate frequency (IF) for wideband CDMA (W-CDMA) transceiver. The majority of the implemented module in hardware is composed of wideband analog-to-digital converters (ADCs), digital-to-analog converters (DACs), and field programmable-gated-arrays (FPGA). And in software, it is coded by VHSIC hardware description language (VHDL) for realizing digital filters and numerically controlled oscillator, etc. To cope with the hardware limitation such as the number of gates in FPGA, the overall digital filter embedded in transceiver is constructed via a cascading a series of decimation and interpolation filters. At transmitter, in order to upconvert the multi-band baseband channels simultaneously, two-stage digital complex quadrature modulation (DCQM) is utilized. The relevant up-and-down conversion of the numerically controlled oscillator (NCO) is designed in the form of a look-up-table (LUT), having samples associated with a sampled sinusoidal with period of 1/4. At receiver, to avoid the usage of surface acoustic wave (SAW) filter, the high-performance digital filter is implemented subject to satisfying band rejection ratio prescribed in blocker and adjacent channel specification. This paper provides the performance of the implemented digital IF module by revealing the results taken from the measurement instruments. Moreover, to confirm its validity computer simulations are simultaneously conducted.
Yoshiharu DOI Seigo NAKAO Yasuhiro TANAKA Takeo OHGANE Yasutaka OGAWA
Research in smart antenna technology has progressed over the past few years and is gradually reaching the phase of practical use. We have developed a smart antenna test bed for wireless local area network (LAN) that is based on the IEEE802.11b. The objective is to improve anti-multipath fading performance and expand communication distance. Using this test bed, we carried out field tests in two environment. One environment is an office in an non line of sight (NLOS), and another environment is an outdoor in a line of sight (LOS). In this paper, we explain the outline of the test bed, the measurement method, and present the results of the field tests. In the office environment, we measured the performance of each set with a different number of antenna elements. The results show that the dead-spots where communication becomes impossible disappear if the number of antenna elements is more than or equal to two. In addition, a greater number of elements indicates better performance. The total average throughput is 1.6 times as efficient when two elements are used, and 1.9 times when four elements are used. Cold spots where the throughput is slower than 1 Mbps are reduced by 80-90%. In the outdoor LOS environment field test, it is shown that by using four-element smart antenna for both transmitter and receiver, the communication distance reached 1km with an average throughput of 4 Mbps. These results prove that the smart antenna drastically improves the performance of a wireless LAN system, i.e. the IEEE802.11b.
Atsushi HONDA Kei SAKAGUCHI Jun-ichi TAKADA Kiyomichi ARAKI
An RF front-end using a six-port circuit is a promising technology for realization of a compact software defined radio (SDR) receiver. Such a receiver, called a six-port direct conversion receiver (DCR), consists of analog circuit and digital signal processing components. The six-port DCR itself outputs four different linear combinations of received and local signals. The output powers are measured at each port, and the received signal is recovered by solving a set of linear equations. This receiver can easily cover a wide frequency band unlike the conventional DCR since it does not require the precise orthogonality that the conventional one does. In this paper, we propose a novel calibration method for a six-port system that includes nonlinear circuits such as diode detectors. We demonstrated the demodulation performance of a six-port DCR by computer simulation and experiments at 1.9, 2.45, and 5.85 GHz.
Under current radio regulations, it is illegal to change the configuration of a radio after its type approval has been acquired. However, the reconfigurability of a Software Defined Radio (SDR) terminal, which is one of its benefits, is possible by changing its software in the field. This contradicts current radio regulations. Therefore, a new authorization procedure is necessary for system reconfiguration using SDR. It is necessary to satisfy the radio regulation. In other words, a new authorization procedure requires techniques to prevent the operation out of the allowed limits of SDR in the field. In this paper, we propose a novel mechanism, called Automatic Certification System (ACS), as a solution to these regulatory issues for SDR. The ACS is a system which gives type approval automatically to the software which affects the output power, central frequency, frequency band, modulation type and which controls analog circuits on an SDR terminal. We also propose the ACS based framework which aims to distribute the burden of the software manufacturer, hardware manufacturer, and governmental authority. After that, we describe the inspection method and discuss the case of a modulation scheme which can be Phase Shift Keying (PSK) or Minimum Shift Keying (MSK) schemes. Our simulations confirm that the ACS is able to certify the modulation software at the terminal.
All-CMOS radio transceivers and systems-on-a-chip are rapidly making inroads on a wireless market that for years was dominated by bipolar and BiCMOS solutions. It is not a matter of replacing bipolar transistors in known circuit topologies with FETs; the wave of RF-CMOS brings with it new architectures and unprecedented levels of integration. What are its origins? What is the commercial impact? How will RF-CMOS evolve in the future? This paper offers a retrospective and a perspective.
Kenta UMEBAYASHI Robert H. MORELOS-ZARAGOZA Ryuji KOHNO
A non-data aided carrier recovery technique using digital modulation format identification called multi-mode PLL (Phase Locked Loop) is proposed. This technique can be interpreted as a modulation identification method that is robust against static phase and frequency offsets. The performance of the proposed technique is studied and the analytical expressions are derived for the probability of lock detection, acquisition time over AWGN channel in the cases of M-PSK and M-QAM modulations with respect to frequency offset and signal-to-noise ratio.
Kei SAKAGUCHI Chih FUNG LAM Tien Dzung DOAN Munkhtur TOGOOCH Jun-ichi TAKADA Kiyomichi ARAKI
A new spectrum management architecture for a flexible software defined radio (SDR) is proposed. In this architecture, the SDR hardware and software are certified separately so as not to destroy the SDR flexibility, but to ensure that any combinations of hardware and software are compliant to the radio regulations even at the system (vertical) handover, global (horizontal) handover, and upgrade (forward) or downgrade (backward) handover. This architecture is based on automatic calibration & certification unit (ACU), built-in GPS receiver, and radio security module (RSM). The ACU is a hardware embedded RF manager that dynamically controls the output power spectrum to be compliant to the local radio regulation parameters. This local radio regulation parameters are securely downloaded to the hardware as an electronic label of the SDR software and stored in the RSM which is a security manager of the hardware. The GPS position check is used, especially during roaming, to keep the compliancy of the terminal to each local radio regulations managed by the geographical region. The principle parties involved in this architecture are telecommunication certification body (TCB), SDR hardware maker (HW maker), SDR software maker (SW maker), and SDR user. The roles and relationships of these four parties in the proposed architecture are clarified in this paper.
Shiann-Shiun JENG Shu-Ming CHANG Bor-Shuh LAN
The software-defined radio technique translates the traditional hardware radio platform to a flexible software radio platform that can support multiple air interface standards. This work proposes an efficient IF processing architecture based on software-defined radio for 2G GSM/IS-95 and 3G W-CDMA systems. Hardware complexity is estimated by fixed-point simulation. IF processing architecture should be highly flexible and minimally complex. Firstly, a carrier channel is selected from a wide frequency band using a high-resolution numerically controlled oscillator (NCO). Wide-range interpolation/decimation is performed by the cascaded integrator comb (CIC) filter that involves no multiplier nor stores filter coefficients. Both the desired narrowband and the desired wideband signals can be extracted. The look-up table (LUT), based on the distributed arithmetic (DA) algorithm is used to implement the finite impulse response (FIR) filter. Therefore, a small area and high speed can be achieved. The errors caused by truncation, quantization, rounding-off and overflow are predicted using a fixed-point simulation. These predictions will help to evaluate the word-length for VLSI implementation. Finally, ALTERA APEX20KE is used as a target device. One hundred thousand gates are used for the implementation. Thus, the proposed architecture has high processing flexibility and small area.
Yasuo SUZUKI Tokihiko YOKOI Yoshimitsu IKI Eiji KAWAGUCHI Nobuo NAKAJIMA Koji ODA Ryoichi HIDAKA
In relation to the Software Defined Radio (SDR) concept, an experimental simulation system was developed. Likewise, verification tests were performed in order to validate the envisaged SDR certification processes including its development, certification, distribution, and software installation assuming the future possibility of exchanging the software in the field.
Hiroshi HARADA Masahiro KURODA Hiroyuki MORIKAWA Hiromitsu WAKANA Fumiyuki ADACHI
The Communications Research Laboratory (CRL) started a new project named the New Generation Mobile Network Project in April 2002. The target of this project is the development of new technologies to enable seamless and secure integration of various wireless access networks such as 3rd and 4th generation cellular, wireless LAN, high-speed mobile wireless, wired communications, and broadcasting networks. This paper presents an overview of CRL's new generation mobile communication system that is called The Multimedia Integrated Network by Radio Access Innovation Plus (MIRAI+), as well as details the role of Software Radio Technology (SDR) in MIRAI+.
Shinya SASAKI Tetsuki TANIGUCHI Yoshio KARASAWA
In this paper, as an important technology for the software-defined radio, a novel scheme of adaptive array antenna utilizing bandpass sampling technique is proposed. For adaptive signal processing, it is necessary to convert the radio frequency signal received by the antenna that is given by real number into baseband region, i.e., complex number region. Then, the method for dividing the bandpass sampled signal to in-phase and quadrature components is analyzed. The sampling scheme is called the IQ-division bandpass sampling. An adaptive array antenna based on the IQ-division bandpass sampling is characterized by the signal processing at the bandpass sampled signal stage, namely, intermediate frequency stage, not baseband. Finally, we will confirm the validity of the proposed scheme through an experiment in a radio anechoic chamber.
Yasuo SUZUKI Hiroshi HARADA Kazuhiro UEHARA Teruya FUJII Yukio YOKOYAMA Koji ODA Ryoichi HIDAKA
This paper presents the summarized achievements of "Study Group on Software Technology for Radio Equipment" held at TELEC from April 2000 to March 2003. The Study Group specified the essential issues on Software Defined Radio (SDR), and discussed desirable methods to evaluate conformity to technical regulations in radios that can change RF characteristics only by changing software. The biggest objective in SDR is to build the architecture to allow users to install software exclusively in the combination of hardware and software that have passed the certification test. The Study Group has reached a solution by introducing the idea of "tally." This paper explains the concept of tally, and proposes two types of systems to use tallies in checking adaptability in combinations of hardware and software.
Yasuo SUZUKI Koji ODA Ryoichi HIDAKA Hiroshi HARADA Tatsuaki HAMAI Tokihiko YOKOI
Interest in the regulatory issues for Software Defined Radio (SDR) is spreading worldwide since the Federal Communications Commission (FCC) recently recognized SDR and created a new category for SDR authorization. SDR technology will bring enormous benefits to the field of wireless services. However, in order to ensure such benefits, revisions of the radio law and/or related ordinances are required regardless of standardization of the software downloading and other implementation details. In order to define the issues peculiar to SDR and to investigate how conformity evaluation should be conducted for radio equipments whose RF characteristics can be altered by software changes in the field, "Study Group on Software Technology for Radio Equipment" was organized by the Telecom Engineering Center (TELEC) in 2000. This paper summarizes a report of the Study Group that was published in March 2003 including the proposal for "Technical regulation conformity evaluation system," the principal output of the study, which proposes how to prevent unauthorized changes to radio equipment in the field.